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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
User’s Manual U15905EJ2V1UD
214
(1) Timers 0 and 1 (TM0 and TM1)
TMn functions as a 16-bit free-running timer or as an event counter for an external signal. Besides being used
for cycle measurement, TMn can be used for pulse output (n = 0, 1).
TMn is read-only, in 16-bit units.
Cautions 1. The TMn register can only be read.
If the TMn register is written, the subsequent
operation is undefined.
2. If the TMCAEn bit of the TMCn0 register is cleared (0), a reset is performed
asynchronously.
TM1
FFFFF610H
0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TM0
FFFFF600H
0000H
Address
After reset
0
TMn performs the count-up operations of an internal count clock or external count clock. Timer start and stop
are controlled by the TMCEn bit of timer mode control register n0 (TMCn0) (n = 0, 1).
The internal or external count clock is selected by the ETIn bit of timer mode control register n1 (TMCn1) (n =
0, 1).
(a) Selection of the external count clock
TMn operates as an event counter.
When the ETIn bit of timer mode control register n1 (TMCn1) is set (1), TMn counts the valid edges of the
external clock input (TIn), synchronized with the internal count clock. The valid edge is specified by valid
edge select register n (SESn) (n = 0, 1).
Caution
When the INTPn0/TIn/TCLRn pin is used as TIn (external clock input pin), disable the
INTPn0 interrupt and set CCn0 to compare mode (n = 0, 1).
(b) Selection of the internal count clock
TMn operates as a free-running timer.
When the internal clock is specified as the count clock by timer mode control register n1 (TMCn1), TMn is
counted up for each input clock cycle specified by the CSn0 to CSn2 bits of the TMCn0 register (n = 0, 1).
Division by the prescaler can be selected for the count clock from among fXX/2, fXX/4, fXX/8, fXX/16, fXX/32,
fXX/64, fXX/128, and fXX/256 by the TMCn0 register (fXX: Internal system clock).
An overflow interrupt can be generated if the timer overflows. Also, the timer can be stopped following an
overflow by setting the OSTn bit of the TMCn1 register to 1.
Caution
The count clock cannot be changed while the timer is operating.
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